1. Technical Field
This invention relates generally to electronic devices, and more particularly, to a method of fabricating a Metal-Insulator-Metal (MIM) device.
2. Background Art
FIG. 1 illustrates a two-terminal metal-insulator-metal (MIM) resistive memory device 30. The memory device 30 includes a metal, for example copper electrode 32, an active layer 34 of for example copper oxide on and in contact with the electrode 32, and a metal, for example copper electrode 36 on and in contact with the active layer 34. As an example of the operational characteristics of such a device 30, with reference to FIG. 2, initially, assuming that the memory device 30 is unprogrammed, in order to program the memory device 30, ground is applied to the electrode 32, while a positive voltage is applied to electrode 36, so that an electrical potential Vpg (the “programming” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32. Upon removal of such potential the memory device 30 remains in a conductive or low-resistance state having an ON-state resistance.
In the read step of the memory device 30 in its programmed (conductive) state, an electrical potential Vr (the “read” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32. This electrical potential is less than the electrical potential Vpg applied across the memory device 30 for programming (see above). In this situation, the memory device 30 will readily conduct current, which indicates that the memory device 30 is in its programmed state.
In order to erase the memory device 30, a positive voltage is applied to the electrode 32, while the electrode 36 is held at ground, so that an electrical potential Ver (the “erase” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the direction of from electrode 32 to electrode 36.
In the read step of the memory device 30 in its erased (substantially non-conductive) state, the electrical potential Vr is again applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32 as described above. With the active layer 34 (and memory device 30) in a high-resistance or substantially non-conductive OFF state, the memory device 30 will not conduct significant current, which indicates that the memory device 30 is in its erased state.
It will be understood that it is highly desirable that the memory device, when programmed, be capable of retaining its programmed state for a long period of time, i.e., until it is desired that the state be changed to its erased state. Likewise, it is highly desirable that the memory device, when erased, be capable of retaining that state for a long period of time as chosen. (these are of particular interest if the device is to be used as a One-Time-Programmable (OTP) device). While the above described device is effective in operation, it has been found that over a period of time, the conductivity of the memory device can be significantly reduced, so that the memory device undesirably loses its programmed state.
Furthermore, it is typical that the formed memory device is subjected to high temperatures during subsequent semiconductor processing steps. It is important that all elements of the memory device be capable of withstanding these high temperatures without degradation in performance. In particular, depending on the material chosen, the active layer can be subject to degradation in performance due to the application thereto of the normal high temperatures involved in subsequent semiconductor processing steps. It is therefore of great interest that the active layer be of a material which is highly effective in operation, meanwhile maintaining high thermal stability.
Therefore, what is needed is an approach wherein these requirements are met.